Posts Tagged big-endian
a piece of assembler code which proves the bug in big-endian mode:
Found the big endian problem: it looks like the memory controller bug.
I managed to launch the CPU in big endian mode, and it even executes
some part of u-boot code. But the serial is silent, and MTD driver can’t find
any NAND chips.
The UART control registers receive correct values, I verified this.
So, most probably the UART hardware fails to get those values from a big-endian CPU.
UPD: Currently the nand_spl loader is compiled in LE, and then it prepares the u-boot image in the memory and switches to BE mode. Then u-boot starts quite normally, but then it hangs up without printing anything to the serial console. Looks like some initialization code breaks internal memory. Need to solder a JTAG connector for further debugging…
I started to port the Armadeus BSP to Big Endian mode. So far, only 5 or 6 files needed to be patched in order to compile everything. But I haven’t started the field tests, as my Armadeus board is still in the ordering process 🙂
Good news, the the guy from Armadeus has got a reply from Freescale:
the big endian it is correct supported by the i.Mx27 since this feature
it is from the ARM9 CORE not from the peripherals, you can see the
information in the ARM web page
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I’m still trying to find a good project, and I think that porting some SBC to Big-Endian architecture would be a useful one. In ipv6 under Little-endian, there’s too much byte swapping for every packet.
Armadeus has got a pretty nice and fresh SoC with a development board. Here’s my message at Armadeus mailing list.
Here are some related articles :
I could not find any benchmark comparison of ipv6 packet processing between big- and little-endian modes. People just say it’s “faster” in BE.
I’ll probably have to do the benchmarking myself, as soon as I find a board that is easy to
switch between LE and BE modes.
Another interesting topic is IPv4/6 acceleration in FPGA…
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